Accelerating Flash Memory Access by Speculative Early Sensing Decision

There are various approaches for reducing Flash access time. NOR Flash enables high speed read access at the cost of a twofold density reduction than NAND and a lower program speed [1]. Throughput improvements include cache read and program [2], but those are efficient for sequential access whereas access patterns can be random [3]. Device approaches include program pulse magnitude optimization [4], but its efficiency decreases with an increase in cell-dimension variability. Architectural approaches include multi-page programming [5], inter-cell interference encoding [6], multiple plains on a chip [7], multi-channel and multi-chip architectures.